1. Field of the Invention
The present invention relates to a semiconductor device having a triple well structure that suppresses the occurrence of a latch-up phenomenon, and to a manufacturing method for such a semiconductor device.
2. Description of the Related Art
A plan view of a semiconductor device 50 constructed with triple well s of the related art is shown in FIG. 4. FIG. 5 shows a cross section of the semiconductor device 50 of FIG. 4 along line A-A.
The semiconductor device 50 is formed on a P-type semiconductor substrate 52. A first N-well 54 doped with N-type impurities is formed in part of a surface region of a main surface of this semiconductor substrate 52. A second P-well 56, doped with P-type impurities, that is shallower than the first N-well 54 is then formed in a surface region of the first N-well 54. A third N-well 58, doped with N-type impurities, that is shallower than the first N-well 54, is then formed in a surface region of the first N-well 54, along the outside of the second P-well 56, where the second P-well 56 is not formed. The impurity concentration of this third N-well 58 is higher than that of the first N-well 54. A fourth P-well 62, doped with P-type impurities, is then formed in a surface region, being the main surface of the semiconductor substrate 52, along the outside of the third N-well 58 where the first N-well 54 is not formed. The impurity concentration of this fourth P-well 62 is higher than that of the semiconductor substrate 52, and has substantially the same impurity concentration as the second P-well 56 and the third N-well 58. In this way, a semiconductor device 50 having a triple well structure is formed. Within this specification, impurity concentration is a concentration of donor impurities or acceptor impurities contributing to carrier generation. Also, a surface region within this specification represents a surface on the semiconductor substrate, and an extremely shallow region in a depth direction of that surface.
Elements are formed in the surface regions of the second P-well 56 and the third N-well 58. For example, NMOS 78 provided with an N-type source region 70, an N-type drain region 72 and a gate 74 is formed in the surface region of the second P-well 56. Also, PMOS 88 provided with a P-type source region 80, a P-type drain region 82 and a gate 84 is formed in the surface region of the third N-well 58.
A P-type P well electrode section 76 is formed in a surface region of the second P-well 56, and connected to an electrode A. This electrode A is held at potential VLOW. Also, an N-type N well electrode section 86 is formed in a surface region of the third N-well 58, and connected to an electrode B. This electrode B is held at a power supply potential VDD. A substrate electrode REF is also provided on the semiconductor substrate 52, and the substrate voltage VREF is held at ground potential.
When using this semiconductor device, the power supply voltage VDD is held at a higher potential than the potential VLOW by control from outside.
Generally, in a semiconductor device having a triple well structure, it is known that a parasitic thyristor is included. In the case of a semiconductor device with this type of parasitic thyristor, there is a problem that a latch-up phenomenon occurs, and an IC containing the semiconductor device is damaged. This problem will now be described.
FIG. 6 shows an equivalent circuit of a parasitic thyristor formed in the semiconductor device 50. There is a parasitic NPN transistor 90, made up of an emitter that is the source region 70 of the NMOS 78, a collector that is the first N-well 54 and a base that is the second P-well 56, and a parasitic PNP transistor 92, made up of an emitter that is the semiconductor substrate 52, a collector that is the second P-well 56 and a base that is the first N-well 54. Inside the second P-well 56, a parasitic resistor 94 is formed between the base of the parasitic NPN transistor 90 and the P-well electrode section 76. A parasitic resistor 95 is also formed inside semiconductor substrate 52, between the emitter of the parasitic PNP transistor 92 and the substrate electrode REF. A parasitic resistor 96 is also formed inside the first N-well 54, between the base of the parasitic PNP transistor 92 and the third N-well 58.
Next, a latch-up phenomenon where the parasitic thyristor is turned on will be described. If low voltage noise is applied to the P-well electrode section 76 and the source region 70 of the NMOS 78, under the influence of the parasitic resistor 94 the base of the parasitic NPN transistor 90 becomes a higher voltage than the emitter, and noise current I1 flows from the base to the emitter. In this way the parasitic NPN transistor 90 is put into an ON state. If the parasitic NPN transistor 90 is put into an ON state, current I2 flows from the collector of the parasitic NPN transistor 90 to the emitter. If current I2 flows, the base voltage of the parasitic PNP transistor 92 is lowered due to the effect of the parasitic resistor 96. As a result of the base of the parasitic PNP transistor 92 becoming a lower voltage than the emitter due to this voltage lowering, current I3 flows from the emitter to the base of the parasitic PNP transistor 92, and the parasitic PNP transistor 92 is put in an ON state. If the parasitic PNP transistor 92 is put into an ON state, current I4 flows from the emitter of the parasitic PNP transistor 92 to the collector. If current I4 flows, current flows to the base current of the parasitic NPN transistor 90 flows, and the parasitic NPN transistor 90 is held in an ON state. As a result, currents I1-I4 continue to flow even if the initially applied noise disappears. Latch-up occurs in this way. Then, once latch-up occurs a large current flows, and there is a possibility of the IC being damaged by the heat generated by latch-up. There have therefore been various schemes up to now for avoiding the occurrence of latch-up.
In order to reduce the occurrence of the latch-up phenomenon, it has been considered to reduce a potential difference between the base and emitter of the parasitic PNP transistor 92 by making the substrate potential VREF lower than the ground potential, so that current I3 does not flow. In this case, however, a large potential difference arises between the third N-well 58 and the adjacent fourth P-well 62. The third N-well 58 and the fourth P-well 62 form a PN junction, and this PN junction is in a reverse-biased state. As long as the potential difference is small, almost no current flows, but if the reverse bias potential difference exceeds a threshold avalanche occurs, and there is a danger of dielectric breakdown.